In modern communications circuitry, digital phase-locked loops (DPLL's) are used to generate output signals having arbitrary frequency by phase locking to a reference signal having a known frequency. To measure the accumulated digital phase of an output signal, the DPLL may employ a counter combined with a time-to-digital converter (TDC). The counter may count the integer portion of the accumulated phase in cycles of the output signal, while the TDC may measure the fractional portion of the accumulated phase.
In conventional DPLL designs, the counter is usually implemented as a synchronous mechanism wherein, e.g., a plurality of D-Q flip-flops is synchronously sampled at every rising edge of the DPLL output signal. Because the DPLL output signal may be a high-frequency signal, this synchronous mechanism may consume a correspondingly high level of power.
It would be desirable to provide a novel DPLL counter design that consumes less power than prior art synchronous counters, while being robust and simple to design.